Method and structure for forming strained devices

ABSTRACT

A method for manufacturing a device includes mapping extreme vertical boundary conditions of a mask layer based on vertical edges of a deposited first layer and a second layer. The mask layer is deposited over portions of the second layer based on the mapping step. The exposed area of the second layer is etched to form a smooth boundary between the first layer and the second layer. The resist layer is stripped. The resulting device is an improved PFET device and NFET device with a smooth boundary between the first and second layers such that a contact can be formed at the smooth boundary without over etching other areas of the device.

FIELD OF INVENTION

The invention generally relates to semiconductor devices and methods formanufacturing such devices, and more particularly to methods for forminga smooth boundary between nitride films to enhance device performanceand product yield.

BACKGROUND DESCRIPTION

Generally, metal-oxide semiconductor transistors include a substratemade of a semiconductor material such as silicon. The transistorstypically include a source region, a channel region and a drain regionwithin the substrate. The channel region is located between the sourceand the drain regions. A gate stack, which usually includes a conductivematerial, a gate oxide layer and sidewall spacers, is generally providedabove the channel region. More particularly, the gate oxide layer istypically provided on the substrate over the channel region, while thegate conductor is provided above the gate oxide layer. The sidewallspacers help protect the sidewalls of the gate conductor.

The current flowing through a channel, which has a given electric fieldacross it, is generally directly proportional to the mobility of thecarriers in the channel. Thus, by increasing the mobility of thecarriers in the channel, the operation speed of the transistor can beincreased. Also, mechanical stresses within a semiconductor devicesubstrate can modulate device performance by, for example, increasingthe mobility of the carriers in the semiconductor device. That is,stresses within a semiconductor device are known to enhancesemiconductor device characteristics.

Thus, to improve the characteristics of a semiconductor device, tensileand/or compressive stresses are created in the channel of the n-typedevices (e.g., NFETs) and/or p-type devices (e.g., PFETs). However, thesame stress component, for example tensile stress or compressive stress,improves the device characteristics of one type of device (i.e., n-typedevice or p-type device) while discriminatively affecting thecharacteristics of the other type device. By way of example, a tensilestress will improve the performance of an NFET and a compressive forcewill improve the performance of a PFET. Thus, in order to maximize theperformance of both NFETs and PFETs within integrated circuit (IC)devices, the stress components should be engineered and applieddifferently for NFETs and PFETs.

To selectively create tensile stress in an NFET and compressive stressin a PFET, distinctive processes and different combinations of materialsare used. For example, a trench isolation structure has been proposedfor forming the appropriate stresses in the NFETs and PFETs,respectively. When this method is used, the isolation region for theNFET device contains a first isolation material which applies a firsttype of mechanical stress on the NFET device in a longitudinal direction(parallel to the direction of current flow) and in a transversedirection (perpendicular to the direction of current flow). Further, afirst isolation region and a second isolation region are provided forthe PFET and each of the isolation regions of the PFET device applies aunique mechanical stress on the PFET device in the transverse andlongitudinal directions.

Alternatively, methods have been proposed for providing a single strainlayer on the entire device, using two lithography masks for patterning.By way of one illustrative example, a single nitride layer with a firststress component is placed over the entire structure, e.g., NFET andPFET, after silicidation. In the example discussed herein, the firstnitride layer imposes a tensile component within the channel of theNFET. An oxide hard mask is then deposited over the nitride layer, and aphoto resist is placed over one of the transistors, e.g., NFET. Areactive ion etching (RIE) is then performed to remove the hard maskover the PFET and the remaining photo resist over the NFET. A nitrideetch is then performed to remove the nitride layer over the PFET.

A nitride layer with a compressive component is then placed over thePFET and the hard mask over the NFET, across a trench isolationstructure (STI). This nitride layer will impose a compressive componentin the PFET to enhance device performance. A photo resist is thendeposited over the nitride layer of the PFET and across the STI. Thisphoto resist also overlaps the tensile nitride layer of the NFET, takinginto consideration only the vertical edge of the first nitride layerduring the mapping process. A nitrogen etching process is thenperformed, which etches away the compressive nitrogen layer overportions of the NFET.

However, due to normal alignment errors of the patterning process, e.g.,placement of the photoresist and difficulties controlling the etching,an overlap of the nitride layers is formed near the boundary of thecompressive nitride layer and the tensile nitride layer. Namely, thecompressive nitride layer remains over portions of the hard mask and thetensile nitride layer over a gate poly and the STI, resulting in threelayers of material. These overlaps result in subsequent etchingdifficulties at this overlap region.

These same alignment errors can also cause gaps between the nitridelayers; however, such a gap is not very desirable because metal ionssuch as Cu can diffuse into silicon from back-end-of-the-line process.Thus, it is very important to ensure that there are no gaps. Toguarantee that there are no gaps, further compensations are made in theetching process so that the nitride layers fill any gaps. Although suchcompensation ensures that the nitride layers will prevent such outdiffusing, a larger overlap can occur.

In further processing steps, an oxide layer is deposited over thenitride layers, and vias are then etched into the oxide layer. A metalis then placed in the vias to create via contacts to the source anddrain regions of the device. However, etching becomes very difficult dueto the variations in layer thickness, especially at the overlap of thenitride layers. For example, etching in the overlap region (i.e., overthe nitride layers and the hard mask layer) to make contact with thedevice results in over etching of the remaining portions of the device.On the other hand, etching designed for the portions of the device withone or two layers will result in an under etch of the overlap region.This under etch will result in a layer blocking contact between thedevice and the contact. (FIG. 1).

While these methods do provide structures that have tensile stressesbeing applied to the NFET device and compressive stresses being appliedto the PFET device, they may require additional materials and/or morecomplex processing, and thus, resulting in higher cost. Further, due tothe inaccuracies of the etching processes, an under etch or over etchcan result in portions of the device. In the case of under etching inthe overlap region, the contact will be blocked from contacting thedevice.

SUMMARY OF THE INVENTION

In a first aspect of the invention, a method for manufacturing a deviceincludes mapping extreme vertical boundary conditions of a mask layerbased on vertical edges of a deposited first layer and a second layer.The mask layer is deposited over portions of the second layer based onthe mapping step. The exposed area of the second layer is etched to forma smooth boundary between the first layer and the second layer. Theresist layer is stripped.

In a second aspect of the invention, the method includes depositing afirst strain layer over a first device and depositing a second strainlayer over a second device and a portion of the first strain layer. Amask layer is deposited over portions of the second strain layer, wherean edge of the mask layer will not exceed extreme vertical boundaryconditions measured from vertical edges of the first strain layer andthe second strain layer. The exposed areas of the second strain layerare etched to form a smooth boundary between the first strain layer andthe second strain layer. The mask layer is then stripped.

In another aspect of the invention, a semiconductor device comprises asemiconductor substrate having at least one p-type device and one n-typedevice. A first strain layer imposes a compressive stress in the p-typedevice and a second strain layer imposes a tensile stress in the n-typedevice. A smooth boundary is provided between the first strain layer andthe second strain layer. A dielectric layer is deposited over the firststrain layer and the second stain layer, including the smooth boundary.A via contact is formed in the dielectric layer and connects to one ofthe n-type device and p-type device at the smooth boundary.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a conventional structure;

FIG. 2 illustrates a beginning structure for forming stress componentsfor a p-type transistor and n-type transistor according to theinvention;

FIGS. 3-8 illustrate exemplary processes for forming stress componentsfor a p-type transistor and n-type transistor according to theinvention;

FIG. 9 illustrates boundary conditions for a resist pattern according tothe invention;

FIGS. 10 and 11 illustrate an exemplary process using one boundarycondition according to the invention;

FIG. 12 illustrates an another boundary condition according to theinvention;

FIGS. 13 and 14 illustrate an exemplary process using the boundarycondition of FIG. 12;

FIGS. 15 and 16 illustrate end processes for forming stress componentsfor a p-type transistor and n-type transistor using the boundaryconditions of either FIGS. 10-11 or FIGS. 12-13 according to theinvention; and

FIG. 17 shows a cross-section of a semiconductor substrate according tothe invention using a scanning electron microscope.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The invention provides a method for fabricating devices with improvedperformance characteristics. In one aspect of the invention, a smoothboundary is formed between two films or layers, i.e., a layer thatimposes a tensile component in an NFET and a layer that imposes acompressive component in a PFET. The smooth boundary does not have gapsor overlaps between the layers. The smooth boundary of the tensile andcompressive films is also critical to improved product yield.

To form a smooth boundary between two stain layers, a resist pattern isaligned to a vertical portion of the second layer, e.g., Si₃N₄, so thata minimum overlap overlay condition of the resist is aligned to theouter surface of the vertical portion of the second nitride layer. Then,an isotopic etch process is applied to remove the second nitride layerfrom the exposed surface and some or all of a vertical portion of thesecond nitride layer that is covered by the resist. In oneimplementation, the second layer is aligned to the first layer patternto provide the smallest overlap possible.

FIG. 2 illustrates a beginning structure for forming stress componentsfor a p-type transistor and n-type transistor according to theinvention. In FIG. 2, a PFET 100 and NFET 200 are formed in aconventional manner in a substrate 102, such as silicon. A gatepolysilicon 104 is formed over a gate oxide 106 on the substrate 102.Source and drain regions 108 and 110 are formed in the substrate 102using known dopants such as arsenic, for example. An oxide spacer 112 isformed on sides of the gate polysilicon 104, with nitride spacers 114formed on the oxide spacers 112. A silicide 116 is formed on the exposedportions of the substrate 102 and on the top of the gate polysilicon104. An STI region 118 is formed between the PFET 100 and NFET 200.

In FIG. 3, a first layer 120 such as, for example, a nitride layer, isformed over the structure of FIG. 2. In the exemplary illustration ofFIG. 2, the first nitride layer 120 generates a tensile stress in theNFET channel in order to enhance the performance of the NFET 200. Thoseof skill in the art should recognize, though, that the first nitridelayer 120 might generate a compressive stress to enhance the performanceof the PFET. In this latter scenario, a tensile nitride layer would thenbe deposited to enhance the performance of the NFET. These layers willbe termed hereinafter “tensile” and “compressive” for sake ofconvenience. In one application using a current 248 nm lithographictool, the first nitride layer is approximately 75 nm with very goodconformality. An oxide hard mask 122 is deposited over the first nitridelayer 120.

FIG. 4 illustrates an exemplary process for forming a photoresist mask123 on the oxide hard mask 122, over the NFET 200. In this exemplaryillustration, the first nitride layer 120 is a tensile nitride layer andthe photoresist mask 123 will protect the tensile nitride layer duringsubsequent etching process. However, in the event that the first nitridelayer 120 is a compressive nitride layer, the photoresist mask 123 wouldthen be placed over the PFET to protect the compressive nitride layerduring subsequent etching process.

FIGS. 5-7 illustrate additional processing steps. FIG. 5 illustrates anoxide etching process in which the oxide hard mask 122 is etch orremoved from the PFET. In FIG. 6, the photo resist mask 123 is strippedto expose the underlying oxide hard mask 122, over the NFET. FIG. 7illustrates a nitride etch to strip the nitride over the PFET 100. Thenitride etch will stop at the silicide layer 116. These processes canequally be used for a compressive nitride layer provided over the PFET,during the initial processing stages.

FIG. 8 illustrates the deposition of a second nitride layer 124. In thisillustration, the second nitride layer 124 is a compressive nitridelayer deposited after the first nitride layer 120 is patterned. In theillustration shown, the thickness of the second nitride layer 124 isapproximately 75 nm with very good conformality. The width of thevertical portion of the second nitride layer 124 is similar to themaximum overlap size, e.g., approximately 70 to 75 nm. In embodiments,vertical film thickness is in a range of alignment error +/−50 nm. Asdiscussed in more detail below, the oxide layer 122 will act as an etchstop during the second nitride etching process.

FIG. 9 illustrates extreme vertical boundary conditions for a resistpattern according to the invention. These extreme boundary conditionsare used to map the edges of the resist layer and to ensure a smoothboundary region between the first nitride layer 120 and the secondnitride layer 124 after etching. As should be understood, though, edgeconditions within the extreme edge conditions can be used in accordancewit the invention to achieve the smooth boundary layer between thenitride layers.

In the example of FIG. 9, a resist layer 126 is formed over the secondnitride layer 124. In designing or mapping this resist layer 126, twoconsiderations are taken in account during the design process: (i) theedge 120′ of the first nitride layer 120 and (ii) the vertical edge 124′of the second nitride layer 124. The distance between the vertical edges120′ and 124′ is considered the inner and outer tolerances of the masklayer 126. In 90 nm or 65 nm technology, the overlay tolerance isapproximately 40 nm, so the maximum overlap of the photo resist isapproximately 80 nm, including the vertical portion of the secondnitride layer 124. The 80 nm dimension provides a slight overlap withthe edge of the first nitride layer 120. These extreme vertical edgeconditions can be adjusted depending on other technologies or otherconsiderations, as should be understood by those of skill in the art.

FIGS. 10 and 11 illustrate the process of providing a smooth boundarybetween the first nitride layer 120 and the second nitride layer 124,using the example of the extreme outer edge 124′. In the process stepsof FIG. 10, an isotropic Si₃N₄ RIE process is used to remove the secondnitride layer 124 in the photo resist 126 opening, as well as laterallybelow the photo resist 126. During this RIE, the oxide layer 122 acts asan etch stop to protect the edge of the first nitride layer 120. FIG. 11illustrates the removal or stripping of the photo resist 126. As shown,these process steps result in a smooth boundary between the firstnitride layer 120 and the second nitride layer 124, e.g., no overlap.

FIGS. 13 and 14 illustrate the process of providing a smooth boundarybetween the first nitride layer 120 and the second nitride layer 124,using the example of the extreme inner edge 120′ shown in FIG. 12. Inthe process steps of FIG. 13, an isotropic RIE process is used to removethe second nitride layer 124 in the photo resist 126 opening. Similar tothat described with reference to FIG. 10, during this RIE, the oxidelayer 122 acts as an etch stop to protect the edge of the first nitridelayer 120. FIG. 14 illustrates the removal or stripping of the photoresist. As shown, these process steps result in a smooth boundarybetween the first nitride layer 120 and the second nitride layer 124,e.g., no overlap.

FIGS. 15 and 16 show end processes for forming the contacts. In FIG. 15,an inter level dielectric 128 is formed over the nitride layers 120 and124. The inter level dielectric 128 may be a deposited TEOS, BPSG or lowK dielectric material. The interlevel dielectric 128 is then planarizedusing, for example, a chemical or mechanical polishing process. As seenin the illustration of FIG. 16, a contact via with a metallizationformed therein, generally represented as reference numeral 130, is thenformed in the interlevel dielectric 128. In the processes describedherein, since there is a smooth boundary between the nitride layers 120and 124, over or under etching is no longer problematic and themetallization properly makes contact with the device.

FIG. 17 shows a cross-section of a semiconductor substrate, manufacturedin accordance with the invention, using a scanning electron microscope.As shown in this illustration, a smooth boundary layer is providedbetween the nitride layers 120 and 124. That is, the smooth boundarylayer is formed as abutting ends of the nitride layers 120 and 124.

In the invention, the NFET and PFET devices are enhanced simultaneouslyusing dual silicon nitride liners. In the invention, the smooth boundarybetween the nitride films will not block the contact to the NFET orPFET. Also, due to the strain engineering, a gap is not formed and metalions will not diffuse into the silicon from BEOL.

While the invention has been described in terms of embodiments, thoseskilled in the art will recognize that the invention can be practicedwith modification within the spirit and scope of the appended claims.

1. A method for manufacturing a device including an n-type device and ap-type device, comprising: mapping extreme vertical boundary conditionsof a mask layer based on vertical edges of a deposited first layer and asecond layer; depositing the mask layer over portions of the secondlayer based on the mapping step; etching exposed areas of the secondlayer to form a smooth boundary between the first layer and the secondnitride layer; and stripping the mask layer.
 2. The method of claim 1,wherein the first layer is a tensile nitride layer formed over then-type device and the second layer is a compressive nitride layer formedover p-type device.
 3. The method of claim 1, wherein the first layer isa compressive nitride layer formed over the p-type device and the secondlayer is a tensile nitride layer formed over the n-type device.
 4. Themethod of claim 1, further comprising forming a hard mask over the firstlayer such that the second layer is formed over the hard mask.
 5. Themethod of claim 1, wherein the hard mask is an oxide hard mask thatprotects a surface and edge of the first layer during the etching step.6. The method of claim 1, wherein the etching step is an isotropicetching.
 7. The method of claim 1, wherein the mask layer is depositedto have an outer edge located within the extreme vertical boundaryconditions.
 8. The method of claim 1, wherein the mask layer isdeposited to have an outer edge located at or near one of the extremevertical boundary conditions.
 9. The method of claim 1, wherein one ofthe extreme vertical boundary conditions of the mask layer overlaps aportion of the vertical edge of the first layer at a junction of thesecond layer.
 10. The method of claim 1, wherein a width of a verticalportion of the second layer is measured from the vertical edge of thesecond layer to approximately the vertical edge of the first layer. 11.The method of claim 8, wherein vertical film thickness is in a range ofalignment error +/−50 nm.
 12. The method of claim 9, further comprising:depositing an interlevel dielectric over the first layer and the secondlayer, including the smooth boundary; etching a via in the interleveldielectric including over the smooth boundary; and placing a contactwithin the via to contact at least one of the n-type device and thep-type device including over the smooth boundary.
 13. A method formanufacturing a device, comprising: depositing a first strain layer overa first device on a substrate; depositing a second strain layer over asecond device on a substrate and a portion of the first strain layer;depositing a mask layer over portions of the second strain layer, wherean edge of the mask layer will not exceed extreme vertical boundaryconditions measured from vertical edges of the first strain layer andthe second strain layer; etching exposed areas of the second strainlayer to form a smooth boundary between the first strain layer and thesecond strain layer; and stripping the mask layer.
 14. The method ofclaim 13, wherein: the first strain layer is a tensile strain layerdeposited on the first device which is a n-type device; and the secondstrain layer is a compressive layer deposited on the second device whichis a p-type device.
 15. The method of claim 13, further comprisingforming a hard mask over the first strain layer to protect a surface andedge of the first strain layer during the etching.
 16. The method ofclaim 13, wherein the etching step is an isotropic etching.
 17. Themethod of claim 13, wherein the mask layer is deposited to have an outeredge located within the extreme vertical boundary conditions, or at ornear one of the extreme vertical boundary conditions.
 18. The method ofclaim 13, wherein: the extreme vertical boundary conditions are mappedto a vertical edge of the second strain layer and a vertical edge of thefirst strain layer; and one of the extreme vertical boundary conditionsof the mask layer overlaps a portion of the vertical edge of the firststrain layer at a junction of the second strain layer.
 19. The method ofclaim 18, wherein a width of a vertical portion of the second strainlayer is measured from the vertical edge of the second strain layer toapproximately the vertical edge of the first strain layer; and adimension of the extreme vertical boundary conditions is approximately80 nm.
 20. A semiconductor device, comprising: a semiconductor substratehaving at least one p-type device and one n-type device; a first strainlayer imposing a compressive stress in the p-type device; a secondstrain imposing a tensile stress in the n-type device; a smooth boundaryprovided between the first strain layer and the second strain layer; adielectric layer deposited over the first strain layer and the secondstain layer, including the smooth boundary; and at least one via contactformed in the dielectric layer and connecting to one of the n-typedevice and p-type device at the smooth boundary.
 21. The device of claim20, wherein the smooth boundary is devoid of gaps.
 22. The device ofclaim 20, wherein the smooth boundary is devoid of overlaps.
 23. Thedevice of claim 20, wherein the at least one via contact is plural viacontacts, the plural via contacts contacting the n-type device andp-type device at the smooth boundary and at locations other than thesmooth boundary.
 24. The device of claim 20, wherein the smooth boundaryis defined as abutting ends of the first strain layer and the secondstrain layer.